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1,187 results

RISC-V International
RISC V as a Software Only Abstraction Layer

Short from the RISC-V Summit North America in 2025. Event Playlist: ...

0:43
RISC V as a Software Only Abstraction Layer

4 views

3 hours ago

Chefi la cuțite
Rebeca Petriman, decizie grea: „Nu vreau să îmi asum acest risc”

ChefiLaCutite #Antena1 Rebeca Petriman, 26 de ani, din Brașov, antrenor personal și fostă campioană națională la dans ...

9:26
Rebeca Petriman, decizie grea: „Nu vreau să îmi asum acest risc”

9,556 views

3 days ago

Mehr Rezon
We are UNBEATABLE as a new duo... 🏆

Use Creator Code: ''REZON7'' to support me for FREE! #EpicPartner MY FORTNITE MAPS ► 1vs1 Map: 7835-3901-1999 ► 2vs2 Map ...

21:45
We are UNBEATABLE as a new duo... 🏆

5,039 views

5 hours ago

LivingLinux
SpacemiT K3 Sherpa-Onnx TTS RISC-V Pre-Release Test

Disclosure: SpacemiT has reviewed this video and they promised me a free SpacemiT K3 board. I agreed to the review, as we are ...

7:27
SpacemiT K3 Sherpa-Onnx TTS RISC-V Pre-Release Test

151 views

2 days ago

ToP Projects Compilation
Most Powerful ESP32 Chip by Espressif?🤯

Espressif has introduced the ESP32-S31, a new high-performance SoC designed for next-generation IoT applications. Alongside ...

8:23
Most Powerful ESP32 Chip by Espressif?🤯

14,038 views

1 day ago

Waveshare Electronics
ESP32-P4 RISC-V Dual-Core + 32MB PSRAM,Integrated 100M Ethernet + PoE Option,MIPI-DSI/CSI #waveshare

Part No. ESP32-P4-ETH ·Description https://www.waveshare.com/esp32-p4-eth.htm?&aff_id=Waveshare The ESP32-P4-ETH is a ...

0:20
ESP32-P4 RISC-V Dual-Core + 32MB PSRAM,Integrated 100M Ethernet + PoE Option,MIPI-DSI/CSI #waveshare

252 views

12 hours ago

RISC-V International
RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays

This talk presents a research journey from energy-efficient RISC-V processor design toward neuromorphic computing ...

52:56
RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays

393 views

3 days ago

Cesar's Hideout
Adding RISC Servers Means More Opportunity for Mistakes in Data Center

I tried running my own data center in Data Center… and yeah, my brain definitely hurts This game lets you build, manage, and ...

36:15
Adding RISC Servers Means More Opportunity for Mistakes in Data Center

1,732 views

3 days ago

Intuition Amiga
IntuitionOS: IExec preemptive multitasking microkernel task switching

Building a microkernel from scratch on a custom CPU. This is IntuitionOS, an Amiga Exec-inspired protected microkernel running ...

1:18
IntuitionOS: IExec preemptive multitasking microkernel task switching

48 views

7 days ago

Decode Circuit
Chiplets & RISC-V Explained: The Future of Hardware

Explore how advanced packaging, chiplets, and the RISC-V architecture are revolutionizing the semiconductor industry and ...

4:39
Chiplets & RISC-V Explained: The Future of Hardware

59 views

3 days ago

Flight Software Workshop
Post Quantum Cryptography for RISC-V Space Systems

Dr. Leonidas Kosmidis (Barcelona Supercomputing Center) presents "Post Quantum Cryptography for RISC-V Space Systems" for ...

22:45
Post Quantum Cryptography for RISC-V Space Systems

27 views

3 days ago

The News Man Podcast
Lucian Florea: "People want success, but they run away from risk" | The News Man Podcast

This episode is supported by Julius Meinl, the traditional Viennese coffee, which invites you to unforgettable discussions ...

1:11:12
Lucian Florea: "People want success, but they run away from risk" | The News Man Podcast

7,974 views

5 days ago

Ellipsis Projects
CPU Control with ROM (RISC-V Part 11)

It's been a while since I last progressed with the RISC-V build. Thanks to all who have stuck with me so far! This time we tackle the ...

11:18
CPU Control with ROM (RISC-V Part 11)

885 views

4 days ago

Austin's BSP Lab
[RISC-V] Trap handler for ECALL instruction exception
4:05
[RISC-V] Trap handler for ECALL instruction exception

27 views

3 days ago

Chip Design with Rashid
RISC-V CPU Design in System Verilog, Video 3, First RTL Simulation: NAND Gate & GTKWave

Here is that readme file mkdir icarus_sim ## Install icarus & gtkwave sudo apt update sudo apt install iverilog gtkwave ## Install ...

20:13
RISC-V CPU Design in System Verilog, Video 3, First RTL Simulation: NAND Gate & GTKWave

106 views

4 days ago

Antena 3 CNN
Risk of food shortage in Romania. Minister: Urgent measures are needed

Food shortage risk in Romania. Minister: Urgent measures needed Read more news and find out the latest information on the ...

2:42
Risk of food shortage in Romania. Minister: Urgent measures are needed

962 views

2 days ago

Spune Adevarul
4 Times Higher Heart Attack Risk? The Invisible Poison That's Destroying Us

We are the first generation to carry our own trash in our veins. It's not a metaphor, it's the reality of 2026. In this ...

7:16
4 Times Higher Heart Attack Risk? The Invisible Poison That's Destroying Us

16 views

4 days ago

Akeana
Akeana RISC-V Architecture Session Vision Summit

Presentation given by Nitin Rajmohan, our co-founder, on Akeana products for AI compute, given at the IESA Vision Summit 2026.

44:21
Akeana RISC-V Architecture Session Vision Summit

23 views

6 days ago

Altitude Addicts
Not Just Made—Russia Is Already Using Its Own Chips Everywhere

Russia is making a major push to rebuild its microelectronics industry, aiming to achieve full technological independence in a ...

10:03
Not Just Made—Russia Is Already Using Its Own Chips Everywhere

13,619 views

6 days ago

Sakshi Kadegiya
RISC vs CISC COA

In this lecture, we explore the fundamentals of Computer Architecture with a focus on two important instruction set designs: RISC ...

12:32
RISC vs CISC COA

31 views

6 days ago